A fast C++ Verilog simulator

Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.

Nombre

verilator

Repositorio

HaikuPorts

Origen de repositorio

haikuports_x86_64

Versión

4.222-1

Tamaño de descarga

55.6 MB

Código fuente disponible

Sí

Categorías

Ninguna

Visitas a la versión

31